1. Technical Field
The present invention relates to a microprocessor, a system including a microprocessor and a method of controlling a bus cycle of a microprocessor. More particularly, it relates to control of a bus cycle and a process of another process request issued while the bus cycle is being executed by the microprocessor.
2. Prior Art
An example of a system including a microprocessor is shown in FIG. 7. FIG. 7 is a block diagram for showing an example of a connection between a microprocessor unit (MPU) 80 and other devices 84, 86 and 88 in a personal computer. The MPU 80 is connected to a bridge chip 82 through a local bus. The local bus is connected to a bus interface unit (BIU) 90 inside the MPU 80 as shown in FIG. 8. The bridge chip 82 executes the mutual conversion between the bus connected with the MPU 80 and buses connected with the other devices 84, 86 and 88. The device 84 connected with the bridge chip 82 through an accelerated graphics port (AGP) bus is a video chip. The video chip 84 is a device for executing the image processing. The device 88 connected with the bridge chip 82 through a memory bus is a memory (storage device). Furthermore, the device 86 connected with the bridge chip 82 through a peripheral component interconnect (PCI) bus is an audio chip. The audio chip 86 is a device for executing the audio processing.
Now, a bus cycle and an interrupt process will be described by exemplifying a case where another process request (hereinafter referred to as an interrupt request) is issued from the audio chip 86 during the execution of a bus cycle for the video chip 84. FIG. 8 shows a flow of signals supplied in the exemplified case (including the bus cycle, a READY signal, an interrupt signal and a bus cycle for the interrupt processing). FIG. 9 is a flowchart for showing procedures in the bus cycle and the interrupt processing. FIG. 10 is a timing chart for showing the signals used in this case (including the bus cycle, the READY signal and the interrupt signal) and an operating status of the interrupt processing. The READY signal used herein is a signal output by a device having received a bus cycle to inform the MPU that the bus cycle can be completed because the requested instruction has been understood or the requested process has been completed. Therefore, when the READY signal is returned, the MPU generates a bus cycle for requesting a subsequent process. Furthermore, it is herein assumed that the process of the audio chip 86 takes priority over that of the video chip 84.
First, the MPU 80 generates a bus cycle for the video chip 84 (S102). Assuming that the image processing of the video chip takes a long period of time, the MPU 80 continuously executes the current bus cycle until the READY signal is returned from the video chip 84 (S104). At this point, the local bus is occupied by the process of the video chip 84. Therefore, as is shown in FIG. 10, when an interrupt request is received from the audio chip 86 during the execution of the bus cycle for the video chip 84, the MPU 80 cannot execute the process requested by the audio chip 86. Accordingly, when the video chip 84 is placed in a ready condition and the READY signal is returned, the bus cycle for the video chip 84 is completed (S106), and the local bus is released. After that, since the interrupt request has been issued by the audio chip 86 (S112); the MPU 80 generates a bus cycle for the audio chip 86 so as to execute the interrupt processing (S114).
When the image processing takes a long period of time in this manner, the process request from the audio chip 86 should be waited until the READY signal is returned from the video chip 84. Since the process of the audio chip 86 lags behind a timing for outputting sound due to this waiting time, it causes the sound to be out of rhythm and a note to be skipped, thus causing various problems. Specifically, in the conventional microprocessor unit 80, even when a process request with high priority is received while waiting for a READY signal, the requested process should be waited until the currently executed bus cycle is completed.
As a method to be adopted in such a case where the process of a device receiving a bus cycle takes a long period of time and a READY signal takes a long time to be returned, a forced termination method or a method of gradually executing a target process is adopted. In the forced termination method, a timer of hardware is used so that the bus cycle can be forcedly terminated when a READY signal is not returned in a predetermined period of time, the microprocessor is informed of a bus time-out error, and the error is processed by using a system program. In this method, however, it is necessary to terminate the currently executed process, and the error processing increases the burden of the software. Alternatively, in the method of gradually executing a target process, accesses to hardware, which require a long waiting time, are not made in a batch, but the process is gradually executed while it is confirmed by the software processing whether the device is in a ready state or not. Also in this method, however, burden of the software is increased, and additionally, the processing speed is decreased because the target process is gradually executed.
An object of the present invention is, in the case where another process request is issued while a microprocessor has issued a bus cycle but a READY signal is not returned for a long period of time, to suspend a currently executed bus cycle so as to priorly execute the requested process.
The microprocessor of the present invention comprises a bus retry detection part for determining whether or not a bus retry signal is externally input and a bus cycle controller for suspending a currently executed bus cycle in response to the bus retry signal detected by said bus retry detection part and for re-starting the suspended bus cycle.
The system including a microprocessor of the present invention comprises a bus retry output device for outputting a bus retry signal and a microprocessor including a bus retry detection part for determining whether or not a bus retry signal is input from the bus retry output device and a bus cycle controller for suspending a currently executed bus cycle in response to the bus retry signal detected by the bus retry detection part and for re-starting the suspended bus cycle.
The method of controlling a bus cycle of a microprocessor of the present invention comprises a bus retry output step of outputting a bus retry signal to a microprocessor and a re-starting step of suspending a bus cycle currently executed by the microprocessor in response to the bus retry signal input to the microprocessor and then re-starting the suspended bus cycle.